1. Field of the Invention
The present invention is related to a semiconductor integrated circuit device and reducing wire delay and skew between wires in the semiconductor integrated circuit device which is arranged with signal wires such as a data bus or address bus which are comprised of a plurality of these wires.
2. Description of the Related Art
In recent years, there has been a tendency for a continuous reduction in wiring pitch with the progress of miniaturization in semiconductor integrated circuit devices, and a situation in which wire delay and skew between wires caused by a significant increase in the amount of capacitance coupling due to narrower spacing between wires and a significant increase in resistance due to a reduction in wire width can no linger be ignored. Since these lead to obstacles to high speed and a reduction in operation margins in a semiconductor integrated circuit device, rapid improvement is being demanded.
In order to reduce wire delay, a method is proposed as is shown in Japanese Laid Open Patent 2000-269447. However, even with this method it is difficult to significantly improve skew between wires without increasing layout size.
The present invention proposes a semiconductor integrated circuit device and a method of arranging wiring in the semiconductor integrated circuit device in which skew between wires can be reduced without increasing layout size while maintaining high speed.